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Hardware-Software Covalidation

A hardware-software system can be defined as one in which hardware and software must be designed together, and must interact to properly implement system functionality. The widespread use of these systems in cost-critical and life-critical applications motivates the need for a systematic approach to verify functionality. In order to manage the complexity of the problem, many researchers are investigating covalidation techniques, in which functionality is verified by simulating (or emulating) a system description with a given test input sequence. The tractability of covalidation makes it the only practical solution for many real designs. A practical difficulty in the validation of hardware-software systems has been the wide gap between the hardware design and the software engineering communities. During the design of a system, lack of communication between hardware and software design groups causes system defects to be discovered late in the design process, requiring costly redesign. Covalidation brings together hardware validation and software testing approaches to address the hardware-software covalidation problem with a uniform approach.

Behavioral Design Validation

Design validation by simulation-based techniques is the most common approach to hardware verification due to the computational complexity of more formal techniques. Validation entails the generation of a test pattern sequence which is applied to the design during simulation to trigger erroneous behavior. Since simulation can only be performed with a small subset of the entire space of test sequences, some method is needed to estimate the degree of verification achieved by a given test sequence. The degree of verification afforded by a test sequence must be known in order to direct test pattern generation, and to provide the designer with the knowledge that verification goals have been achieved. Research in software testing has produces several validation metrics which operate at the behavioral level, including simple metrics such as statement and branch coverage, as well as more complex metrics based on mutation and dataflow analysis. We are investigating the application of software testing metrics to measure hardware validation coverage. We are also developing metrics to enable the detection of faults associated with concurrency and timing.

Testing of FPGA Architectures

As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. The high density local interconnect serves to improve FPGA utilization, but also greatly complicates the FPGA interconnect testing problem. We have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect faults to be detected. This technique is applicable to any cluster-based FPGA architecture and enables the detection of bridging faults involving intra-cluster interconnect and extra-cluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intra-cluster configurations separately from extra-cluster configurations, thereby improving the efficiency of the configuration definition process. By guaranteeing that both intra-cluster and extra-cluster configurations have several test transparency properties, hierarchical fault detectability is ensured.